1. Field
The present application relates to a semiconductor device and a method of estimating capacitance value.
2. Description of the Related Art
In development of semiconductor devices in recent years, a finer process, higher integration, a faster operating frequency, and a lower power supply voltage have been promoted. Since power supply noise is caused by the operation of instances formed in a conventional semiconductor device, logical malfunction, and malfunction due to timing shift are significant when higher speed and lower voltage are achieved. In a stage of design, an apparatus used in association with designing the conventional semiconductor device estimates the total power consumption of logic cells placed in a target region, and places decoupling capacitors corresponding to the total power consumption, in the target region and near target instances, in a dispersed manner.
The conventional semiconductor device includes a plurality of types of instances coupled to each other. In the instances, the power supply voltage fluctuation amount that affects operation is different. In other words, the noise tolerance of the instances is different.
According to a conventional method for designing the conventional semiconductor device, the capacitance value of decoupling capacitors is greater than a capacitance value required for the configuration of the semiconductor device. Many decoupling capacitors formed in the conventional semiconductor device increase the chip area required for the conventional semiconductor device.